1. Field of the Invention
The present invention generally relates to a probe card, and more particularly to a probe card used for measurement in a test for electrical performance of a semiconductor device in a wafer state and chip state during its production process. In particular, the present invention relates to a probe card used for testing a semiconductor power device in a wafer state and chip state.
2. Description of the Prior Art
A semiconductor power device is generally subject to a three-stage test including a wafer test, chip test and final test before it is shipped to a user. The wafer test is performed in a wafer state, while the chip test is performed in a chip state after the wafer is diced. The final test is performed after the chip of the power device is incorporated into a mold to be assembled into a module and before it is shipped to a user.
The wafer test and chip test are performed in order to prevent possible inflow of defective chips in an assembling process, i.e., in order to best reject possible defective chips in a chip state.
This is because the production cost can be suppressed lower on the whole with the more reduced inflow of defective chips in the assembling process. On the contrary, increased rate of the inflow of defective chips in the assembling process requires a discard of not only a defective chip but also a module itself. Specifically, even incorporated non-defective chip or other non-defective elements are required to be discarded. Accordingly, the production cost is increased on the whole. Therefore, it is important to enhance a precision in rejecting defective chips during the wafer test and chip test in order to reduce the production cost.
Further, the wafer test and chip test have to be performed under a condition close to the final test for enhancing the precision in rejecting defective chips during these tests. In particular, since the power device has a great current capacity, it is required to be tested with high current as great as possible in the wafer test and chip test.
A probe card is generally used for performing the wafer test or chip test. There is a limitation on current capacity flowing per one spring probe needle (hereinafter referred to as xe2x80x9cpinxe2x80x9d or xe2x80x9cneedlexe2x80x9d) made of tungsten or the like mounted on the probe card. Therefore, in the case where current exceeding the limitation is required to flow, a plurality of pins (or needles) are electrically short-circuited for use. Specifically, as shown in FIG. 9, a plurality of pins (or needles) electrically short-circuited for use are brought into contact with the same electrode pad of the semiconductor device chip.
FIG. 9 is an equivalent circuit diagram of a conventional probe card configuration, wherein n pieces of pins (or needles) are brought into contact with a pad surface 91 of a chip, and a current I is applied to flow through the pins. In this figure, P1, P2, P3, . . . PN represent each pin (or needle), while r1, r2, r3. . . , rn indicate each contact resistance between these pins (or needles) and the pad of the chip.
However, the above-mentioned conventional probe card has problems as to be described below. Specifically, the first problem is such that, even if a plurality of pins (or needles) are brought into contact with the same pad 91 in order to flow a high current as shown in FIG. 9, a deviated flow occurs in current flowing through each pin (or needle), since the respective contact resistances r1, r2, r3. . . , rn are not uniform.
Specifically, the variation in current flowing through each pin (or needle) is influenced by the variation of the contact resistances between each pin (or needle) and the pad. The current is concentrated on the pin having the smallest contact resistance, which results in that this pin (or needle) is broken down. When one pin is broken down, the current is then concentrated on the one having the second smallest contact resistance. As a result, a breakdown of pins may occur one after another.
As described above, concentration of current on a part of the pins (or needles) entails problems of a burnout of the pad of the chip, a burnout of pins (or needles), or concentrated current in a part of the pad, resulting in that a test cannot be measured with high precision.
In order to solve the above-mentioned problems, Japanese Patent Unexamined (Laid-open) Publication No. 60-142526 (1985) discloses a technique such that each contact resistance is provided between a semiconductor device to be tested for its electrical performance and each of the plural pins (probe needles) on a probe card, and that resistances greater than each contact resistance are inserted to each pin in series. This arrangement equalizes current values flowing though the pins, thereby preventing a breakdown of a pin during the test measurement. The resistance inserted in series in each pin for well-balanced flowing of high current is referred to as xe2x80x9cbalance resistancexe2x80x9d in the following explanation.
This conventional technique discloses a method for well-balancedly carrying a high current through each pin, but it has no teaching about a check method for checking whether each pin on the probe card has a defect or not. Accordingly, there has been a problem in bringing the conventional technique into practical use.
There is a second problem such that, a pin (or needle) on a probe card has stains or the like attached on a tip end thereof while it is repeatedly used for a performance test of a semiconductor device, resulting in that a contact resistance between the tip end of the pin and a testing pad section varies and in some cases a spring characteristic of the pin is deteriorated to thereby increase a contact resistance.
The variation in the contact resistance brings an incorrect measurement result of a performance test of a semiconductor device. Therefore, a regular check of pins (or needles) on a probe card is required for checking in daily life whether a defect is present or not on each pin (or needle). If a pin having some defect is observed, this defective pin should be replaced.
In FIG. 10, a probe card checker (shown by a reference numeral 101) is used for checking a pin (or needle) on a probe card. Specifically, as shown by a probe card checker disclosed in Japanese Patent Unexamined (Laid-open) Publication No. 8-299210 (1996), a pin (or needle) on a probe card is brought into elastic contact with a metal plate of the checker for measuring an electrical resistance between the metal plate and a connector electrode of the probe card, whereby an abnormal state of each pin (or needle) can be checked.
In this method, however, in the case where a plurality of pins (or needles) are brought into contact with the same pad for causing an electrical short-circuit as shown in FIG. 10, the contact resistances between all pins (or all needles) and a metal plate 102 for checking the probe card are connected in parallel. Therefore, this technique has a problem that, even though the abnormal state of the entire pins (or needles) can be checked, a check as to whether there is an abnormal state on a part of or individual pin (or needle) cannot be performed.
Further, Japanese Patent Unexamined (Laid-open) Publication No. 5-347335 (1993) discloses a technique of providing in series on-off change-over switches on each probe needle. Only a switch on a probe needle to be checked is turned on upon checking a probe needle while the other switches are turned off, so that a check per one probe needle can be performed.
However, when a balance resistance for flowing a high current is connected to each probe needle, the balance resistance enters in series upon checking each probe needle, thereby being unable to check in this configuration. Therefore, this configuration cannot be applied to a probe card to which a balance resistance for a high current is mounted.
Japanese Patent Unexamined (Laid-open) Publication No. 6-120313 (1994) discloses a technique such that another probe needle for checking a contact state of a probe needle is provided separate from a probe needle for testing a chip in order to check the probe needle during a wafer test. The disclosure shows that a resistance between these probe needles is measured to check whether a contact defect of the probe needle is present or not.
However, when a balance resistance is connected to each probe needle, the balance resistance enters in series upon checking each probe needle, thereby being unable to check in this configuration. Therefore, this configuration cannot be applied to a probe card to which a balance resistance for high current is mounted.
The present invention has been made to solve these problems and has an object to provide a probe card wherein, in the case where a plurality of probe pins are electrically short-circuited for use, well-balanced current can be flown through each probe pin to prevent a burnout of a chip pad as well as a burnout of the probe pins due to concentrated current flow on a part of the pins, thereby enhancing a measuring precision of a test, and further even if a plurality of probe pins are electrically short-circuited for use, confirmation can individually be made as to whether each of the probe pins has a defect or not.
Additionally, the present invention aims to provide a probe card that can individually check as to whether each probe pin has a defect or not in a normal probe card substrate, even in the case where connector electrodes for checking a contact with a chip is lacking in number.
Further, the present invention aims to realize an improved probe card with use of a conventional probe card checker as it is.
In order to attain the above-mentioned objects, a probe card according to the present invention is used in a performance test of a chip of a semiconductor device in a production process of the semiconductor device. The probe card includes a plurality of probe pins for flowing a high current therethrough for the test. Each of the probe pins has a balance resistance connected thereto in series, and a each balance resistance is greater in value than a contact resistance which is produced between each of the probe pins and a chip pad of the semiconductor device when contacted with each other.
A plurality of contact check wires are respectively connected to the probe pins for checking a contact performance of each of the probe pins, wherein each of the contact check wires is drawn from a junction point positioned between each of the probe pins and a corresponding balance resistance connected thereto.
By this configuration, a high applied current can be well-balanced to flow through each probe pin, to thereby prevent a burnout of a chip pad as well as a burnout of the probe pins due to concentrated current flow on a part of the probe pins, Thus, a measuring precision of a test can be improved, and further makes it possible to individually check as to whether each probe pin has a defect or not even in the case where a plurality of the probe pins are electrically short-circuited for use.